A trap flag permits operation of a processor in single-step mode. If such a flag is available, debuggers can use it to step through the execution of a computer program.

Single-step interrupt

When a system is instructed to single-step, it will execute one instruction and then stop. The contents of registers and memory locations can be examined; if they are correct, the system can be told to go on and execute the next instruction. The Intel 8086 trap flag and type-1 interrupt response make it quite easy to implement a single-step feature in an 8086-based system. If the trap flag is set, the 8086 will automatically do a type-1 interrupt after each instruction executes. When the 8086 does a type-1 interrupt, it pushes the flag register on the stack.


The 8086 has no instruction to directly set or reset the trap flag. These operations are done by pushing the flag register on the stack, changing the trap flag bit to what the programmer wants it to be, and then popping the flag register back off the stack. The instructions to set the trap flag are: PUSHF ; ''Push flags on stack'' MOV BP,SP ; ''Copy SP to BP for use as index'' OR WORD PTRP+00100H ; ''Set TF flag'' POPF ; ''Restore flag Register'' Actually you do not use the Trap flag in this way, because you are normally monitoring a program from an Interrupt Service Routine (ISR). You continue execution of the program by an IRET. Int3ServiceRoutine: ; ''Stack: Ret, Flags'' PUSHA ; ''Stack: Ret, Flags, AX, CX, DX, BX, SP, BP, SI, DI'' PUSH DS PUSH ES ; ''Stack: Ret, Flags, AX, CX, DX, BX, SP, BP, SI, DI, DS, ES'' ''... the ISR code'' using only integer (otherwise you must also store floating point registers) MOV BP,SP ; ''Stack: Ret, Flags, AX, CX, DX, BX, SP, BP, SI, DI, DS, ES'' MOV BP,P+10'' ; ''Stored SP'' OR WORD PTRP+00100H ; ''Set TF flag in the stored Flag register'' POP ES POP DS POPA IRET ; ''continue execution for ONE instruction, then calling ISR again.''


To reset the trap flag, simply replace the OR instruction in the preceding sequence with the instruction: :AND WORD PTRP+00FEFFH The trap flag is reset when the 8086 does a type-1 interrupt, so the single-step mode will be disabled during the interrupt-service procedure. {| class="wikitable" style="font-size:88%;" |- | {| style="font-size:88%;" |- |colspan="17" | Status register |- |style="width:10px" align="center" | 15 |style="width:10px" align="center" | 14 |style="width:10px" align="center" | 13 |style="width:10px" align="center" | 12 |style="width:10px" align="center" | 11 |style="width:10px" align="center" | 10 |style="width:10px" align="center" | 9 |style="width:10px" align="center" | 8 |style="width:10px" align="center" | 7 |style="width:10px" align="center" | 6 |style="width:10px" align="center" | 5 |style="width:10px" align="center" | 4 |style="width:10px" align="center" | 3 |style="width:10px" align="center" | 2 |style="width:10px" align="center" | 1 |style="width:10px" align="center" | 0 |style="width:160px; background:white; color:black" | (bit position) |- |- style="background:silver;color:black" |style="width:10px" align="center" | - |style="width:10px" align="center" | - |style="width:10px" align="center" | - |style="width:10px" align="center" | - |style="width:10px" align="center" | O |style="width:10px" align="center" | D |style="width:10px" align="center" | I |style="width:10px" align="center" | T |style="width:10px" align="center" | S |style="width:10px" align="center" | Z |style="width:10px" align="center" | - |style="width:10px" align="center" | A |style="width:10px" align="center" | - |style="width:10px" align="center" | P |style="width:10px" align="center" | - |style="width:10px" align="center" | C |style="width:160px; background:white; color:black" | Flags Category:Central processing unit Category:Debugging